1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device allowing an increased number of such devices to be tested simultaneously.
2. Description of the Background Art
A memory tester TST for testing semiconductor memory devices as shown in FIG. 23 includes a motherboard MBD. Motherboard MBD has a plurality of mounting portions 51 for respectively mounting a plurality of chips thereon, and a connecting portion 52 corresponding to the memory tester side. The number of chips to be mounted onto motherboard MBD is determined according to the number of I/Os that is limited by memory tester TST.
Conventionally, for a chip of dynamic random access memory (DRAM) of x32-bit configuration, the number of testable I/Os is 32. Memory tester TST limiting the number of I/Os to 64 can test two such chips at the same time.
However, if the number of input/output terminals being used increases due to an increase of memory integration or a change of interfaces, the number of chips for simultaneous testing has to be reduced. This decreases productivity of the semiconductor memory devices like DRAMs.
Accordingly, an object of the present invention is to provide a semiconductor memory device allowing an increased number of chips to be tested simultaneously.
The semiconductor memory device according to the present invention is a semiconductor memory device that allows selection of desired one of a plurality of word configurations. The semiconductor memory device includes: a test mode recognition circuit that inactivates a test mode signal in a normal operation mode and activates the test mode signal in response to an externally supplied test mode designating signal; a word configuration select circuit that selects, from a plurality of word configurations, a word configuration for use in the normal operation mode when receiving the inactive test mode signal from the test mode recognition circuit, and selects, from the plurality of word configurations, a word configuration that is smaller than that for use in the normal operation mode when receiving the active test mode signal from the test mode recognition circuit; and a terminal that inputs/outputs data to/from a memory cell array based on the word configuration selected by the word configuration select circuit.
According to the semiconductor memory device of the present invention, when the test mode signal is activated, the test is conducted selecting the word configuration that is smaller than that for use in the normal mode. Thus, a larger number of semiconductor memory devices can be mounted on a testing device and tested at the same time. As a result, it becomes possible to improve the throughput of testing of semiconductor memory devices.
Preferably, the semiconductor memory device further includes a word configuration determination signal generating circuit that generates a first word configuration determination signal when the inactive test mode signal is input from the test mode recognition circuit, and generates a second word configuration determination signal when the active test mode signal is input from the test mode recognition circuit. The word configuration select circuit selects the word configuration for use in the normal operation mode according to the first word configuration determination signal, and selects the word configuration that is smaller than that for use in the normal mode according to the second word configuration determination signal.
According to the semiconductor memory device of the present invention, when the test mode signal is activated, the test is conducted utilizing the word configuration that is smaller than that for use in the normal operation mode. Thus, it becomes possible to simultaneously mount a larger number of semiconductor memory devices on a testing device for testing. This improves the throughput of testing of semiconductor memory devices.
Still preferably, when the test mode signal is active, the word configuration determination signal generating circuit selects as a word configuration of the semiconductor memory device, the smallest word configuration from those selectable.
The test is thus conducted selecting the smallest possible word configuration. Accordingly, a maximum number of semiconductor memory devices can be mounted on the testing device, thereby maximizing the throughput of testing of the semiconductor memory devices.
The semiconductor memory device according to the present invention includes: mxc3x97n output terminals consisting of n short-circuited terminal groups each having m terminals being short-circuited in a test mode; a test mode recognition circuit that inactivates a test mode signal in a normal operation mode and activates the test mode signal in response to an externally supplied test mode designating signal; an output terminal select signal generating circuit that generates, when the test mode signal is active, a first output terminal select signal for causing data to be output from n output terminals each selected from respective one of the n short-circuited terminal groups, and generates, when the test mode is inactive, a second output terminal select signal for causing data to be output from the mxc3x97n output terminals; and an output terminal select circuit that selects either the n output terminals or the mxc3x97n output terminals according to the first or the second output terminal select signal generated.
For testing the semiconductor memory device having mxc3x97n output terminals, n output terminal groups are arranged, in each of which m output terminals are being short-circuited. Each one output terminal is selected from respective one of the n output terminal groups, and the n output terminals thus selected are used for the test. Accordingly, the semiconductor memory device can be tested with the number of output terminals reduced from mxc3x97n to n. As a result, it becomes possible to increase the number of semiconductor memory devices that can be mounted on the testing device simultaneously.
Preferably, the test mode recognition circuit inactivates all of m test mode signals in the normal operation mode, and activates any one of the m test mode signals in response to an externally supplied test mode designating signal. The output terminal select signal generating circuit generates, according to the m test mode signals, first and second output terminal select signals each made of m output terminal select signals. More specifically, when any one of the m test mode signals is activated, it generates the first output terminal select signal in which only one of the m output terminal select signals corresponding to the activated test mode signal is activated. When all the m test mode signals are inactivated, it generates the second output terminal select signal with all the m output terminal select signals being activated. The output terminal select circuit, when receiving the first output terminal select signal, selects n output terminals corresponding to the activated one of the m output terminal select signals.
Thus, the m output terminal select signals are generated corresponding to the m test mode signals. In the test mode, any one of the m test mode signals is activated, and the remaining test mode signals are inactivated. In response, only one output terminal select signal corresponding to the activated test mode signal is activated, and in turn, n output terminals are selected corresponding to the activated output terminal select signal. An output terminal select signal to be activated is changed by altering the one test mode signal to be activated among the m test mode signals. Different n output terminals are thus selected corresponding to the change of the output terminal select signal being activated. Meanwhile, in the normal operation mode, all the test mode signals are inactivated, the m output terminal select signals are all activated, so that the mxc3x97n output terminals are all selected.
As described above, every m output terminals are short-circuited to form n output terminal groups, and each one output terminal is selected from respective one of these n output terminal groups. Thus, n output terminals not short-circuited with each other are configured. The combination of these n, non-short-circuited output terminals changes sequentially for testing the memory cells. As a result, the test can be conducted with the number of output terminals being reduced from mxc3x97n to n, so that the number of semiconductor memory devices that can be simultaneously mounted on the testing device increases.
Preferably, the output terminal select circuit includes mxc3x97n output circuits connected to the mxc3x97n output terminals respectively. When the first output terminal select signal is input, the output terminal select circuit simultaneously activates n output circuits that correspond to the activated output terminal select signal.
The n output circuits being connected to the n output terminals selected in the test mode are simultaneously activated, so that data are output from the n output terminals. Accordingly, the data output from the n output terminals can be examined simultaneously, thereby allowing rapid testing.
Preferably, the semiconductor memory device further includes: a word configuration determination signal generating circuit that generates a word configuration determination signal for determining one word configuration from a plurality of word configurations; and a word configuration select circuit that selects a word configuration according to the word configuration determination signal. The number of the test mode signals is determined according to the word configuration selected by the word configuration select circuit.
In response to the determination of the word configuration, the number of the test mode signals is determined to conform to the word configuration. Accordingly, the test mode signals controlling the test mode can be generated in conformity with the word configuration. This allows precise testing.
Still preferably, the semiconductor memory device further includes an interface that inputs a data mask signal. The output terminal select signal generating circuit generates the first and the second output terminal select signals according to the test mode signal and the data mask signal.
When the semiconductor memory device externally receives the data mask signal along with the test mode designating signal, the first output terminal select signal, for selecting n non-short-circuited output terminals by selecting each one output terminal from-respective one of the n output terminal groups each including m short-circuited output terminals, or the second output terminal select signal, for selecting the mxc3x97n output terminals, is generated based on the test mode signal and the data mask signal. Accordingly, it is possible to control the test mode using the data mask signal for use in the normal operation mode.
Preferably, the semiconductor memory device further includes: a word configuration determination signal generating circuit that generates a word configuration determination signal for determining one word configuration from a plurality of word configurations; and a word configuration select circuit that selects a word configuration according to the word configuration determination signal. The output terminal select signal generating circuit generates first and second output terminal select signals each made of a plurality of output terminal select signals. The number of output terminal select signals forming each of the first and second output terminal select signals is determined based on the word configuration selected by the word configuration select circuit.
When the word configuration is determined, the output terminal select signals are determined with its number conforming to the word configuration. Thus, the number of output terminal select signals for selecting output terminals for use in the test mode can be reduced, thereby allowing efficient testing.
Preferably, the semiconductor memory device includes: a word configuration determination signal generating circuit that generates a word configuration determination signal for determination of one of a plurality of word configurations; a test mode recognition circuit that inactivates a test mode signal in a normal operation mode and activates the test mode signal in response to an externally supplied test mode designating signal; a driver select/drive signal generating circuit that generates a driver select/drive signal for selecting and driving a write driver for use in writing data into a memory cell array, according to a column address signal prohibited in the normal operation mode, the test mode signal and the word configuration determination signal; and m write drivers that are respectively connected to m input/output terminals being short-circuited in the test mode. When the test mode signal is activated, the word configuration determination signal generating circuit generates a word configuration determination signal for fixing the word configuration of the semiconductor memory device to the word configuration for use in the normal operation mode, and the driver select/drive signal generating circuit generates the driver select/drive signal for selecting and driving the m write drivers one by one.
For the m input/output terminals being short-circuited in the test mode, such short-circuited conditions are cancelled and data are written into respective input/output terminals. Thus, even for the input/output terminals which are short-circuited in the test mode and for which cross interference due to the data writing cannot otherwise be measured, it becomes possible to examine such interference due to the data writing, thereby enabling accurate testing.
Preferably, the driver select/drive signal generating circuit generates a driver select/drive signal that allows switching of write drivers being selected and driven, based on the column address signal.
The column address signal is used to cancel the short-circuited conditions of the m input/output terminals being short-circuited in the test mode, and data are written via respective input/output terminals. Thus, data writing in the test mode can be controlled utilizing the column address signal that is prohibited in the normal operation mode.
Preferably, the semiconductor memory device further includes: mxc3x97n input/output terminals consisting of n short-circuited terminal groups each having m terminals being short-circuited in the test mode; an output terminal select signal generating circuit that generates, when the test mode signal is active, a first output terminal select signal for outputting data from n input/output terminals each of which is selected from respective one of the n short-circuited terminal groups, and generates, when the test mode signal is inactive, a second output terminal select signal for outputting data from the mxc3x97n input/output terminals; and an output terminal select circuit that selects, according to the first or second output terminal select signal, the n input/output terminals or the mxc3x97n input/output terminals.
For testing the semiconductor memory device, the short-circuited conditions of the m input/output terminals being short-circuited in the test mode are first cancelled, and data are written via respective input/output terminals. Each one output terminal is selected from respective one of the n output terminal groups each having m short-circuited terminals, and data are read out using thus selected n output terminals not short-circuited with each other. Accordingly, the cross interference among the m input/output terminals being short-circuited in the test mode can be examined with the number of input/output terminals being reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.